Overview of the Hardware Lab Environment
The workstations in the Hardware Lab (Briggs 222) are all configured to run Ubuntu Linux and are all identically configured to have the Intel FPGA development toolchain installed on them. These machines all share the same filesystem, which means that anythings saved on one workstation will be there if you continue your work later on another machine.
To login to one of the lab machines, just type in your Rhodes user ID and usual password when prompted. It may take a moment to log you in the first time.
Running the Intel / Altera Quartus Software
Once you are logged in, you should see a desktop as shown below. To run Quartus, click on the grid icon that is pointed to by the red arrow.
This should bring up a search dialog box. Just start typing “Quartus” and you should see something similar to the following screen:
Click on the Quartus icon and give it a moment. Quartus is a complex piece of software and it make take 10-20 seconds for it to start. Try to avoid the temptation to start multiple instances of Quartus – not good.
After a short bit, you should see a splash screen and the IDE should come up as shown in your class project documentation. Sometimes, when launching Quartus it will show you this dialog box:
Quartus is a commercial software product that is used by industry hardware engineers. Developing production hardware requires a number of features far beyond the scope of your coursework, so we don’t need them. The basic (Lite) version of Quartus is free for academic use, this dialog is just asking us whether we want to use the Lite version or pay $3K for a full license. Select the option shown and click OK.
Running the Monitor Program
Similar to finding Quartus above, just click the grid icon to bring up the search dialog and start typing “Altera”. If you see the icon for the program (it looks like an integrated circuit chip), click it and it should launch the Altera Monitor Program.
Troubleshooting
Quartus Issues
Common Schematic Problems
Several common mistakes can cause problems with either your circuit compiling at all, or working properly when it does compile. Here is a short list of things to check if you are having issues:
Construction Order – It’s usually easiest to get things correct if you build your circuit with the logic elements (gates, inputs, outpus) first then go and connect them with wires.
Cutting and Pasting – Be cautious with cutting and pasting, especially when there are existing wires where you are pasting. It is not a guarantee that your pasted element will be connected to the wire or not automatically connected to a wire in the pasted area. It’s best to remove wire segments in the pasted area, paste your logic element, then reconnect it with the wire tool.
Unconnected Wires – Make sure that your wires are actually connected to the input/output or gate wires. If you move a logic element, the connected wires should move as you move around the logic gate. (Hit undo if you drop the moved gate into a bad place)
Short-Circuited Wires – This is a particularly nasty issue because it’s tricky to see in the editor. This can usually be avoided by following the construction orders and cut/paste rules above. Sometimes you may drag the wire tool and it will make a junction with another wire that is unwanted. If you can’t figure out where the short is located, you can double-click on the error message. It should take you to at least the correct file and wire. If you can’t find the short, it’s usually easiest to delete all of the related connections and re-do them, ensuring that no short circuits are introduced.
Cannot Query JTAG Chain
JTAG is the protocol that runs over the USB cable to configure the FPGA from the workstation. There are two basic issues that students commonly have if there are JTAG issues.
Incorrect Device Configuration – If your Quartus project is configured with the incorrect device information, it won’t work with the actual FPGA hardware. The JTAG protocol is looking for a specific match and if you have the wrong device type or used “Auto device selected by the Fitter” in your project setup, this needs to be corrected. Go to Assignments->Device… and verify that you have selected the correct FPGA device.
JTAG Server Connection – When Quartus starts, it also starts another program called a JTAG server which acts as the broker between the PC and FPGA. Sometimes this can get stuck or otherwise die. If you are brave enough to open a terminal you can check to see if everything is running properly by running the
jtagconfigcommand. It should look something like this:
If this command hangs or prints out an error, you have an issue with the JTAG server. This can usually be solved by exiting out of Quartus and re-starting it. If that doesn’t work, unplug the FPGA from the USB cable, restart the workstation, login, and restart Quartus. Once it’s running, plug in the FPGA and try again.
instX Is Already Defined
When you create a circuit using the schematic editor, Quartus is translating these logic schematics to programs in Verilog or VHDL. Each gate is given a variable name, which is shown in the schematic editor. This error occurs when cutting/pasting circuits or Quartus gets otherwise confused. It basically means that two logic elements have the same variable name, which causes problems with the Verilog/VHDL compiler. Look through your circuit for this scenario:
Here we can see two AND gates both have the same variable name inst1. The fix is straightforward, just right-click on one of the gates and give it a unique name.
Time-Limited SOF Dialog Box
You should not close this dialog – just move it out of the way. The Nios CPU is also sold for commercial use. It is free to use as long as the FPGA is plugged into the USB port for the workstation, but will deactivate after 60 minutes of being unplugged. Since we never unplug the development board, this isn’t a concern (unless you click the Disconnect button).
Monitor Program Issues
Compile & Load Fails
If you get an error that states something like “could not make target compile", this is a known issue with the Monitor Program. There is a script which should fix it, but it only runs when you start the Monitor Program. If you have this error, try quitting the Monitor Program and restarting it. This should fix the issue.
Time-Limited SOF Dialog Box
You should not close this dialog – just move it out of the way. The Nios CPU is also sold for commercial use. It is free to use as long as the FPGA is plugged into the USB port for the workstation, but will deactivate after 60 minutes of being unplugged. Since we never unplug the development board, this isn’t a concern (unless you click the Disconnect button).